The invention relates to a compensation circuit for a digital/analogue converter.
FIG. 1 shows a conventional digital/analogue converter which is clocked by a clock signal CLK. The digital/analogue converter converts a digital data signal originating from a data source into an analogue output signal. The clock signal CLK is generated by a PLL circuit (phase-locked loop). The clock signal has a jitter in the time interval, i.e. the time interval of the clock pulse edges varies slightly from clock pulse period to clock pulse period. The clock jitter causes undesirable high-frequency signal distortions during the digital to analogue conversion. In the conventional circuit arrangement shown in FIG. 1, these distortions are suppressed by generating a clock signal having a very low jitter. For this purpose it is necessary to use clock signal sources such as the LC-PLL circuit shown in FIG. 1, which generates a low-jitter clock signal. The greater the resolution of the digital/analogue converter, the higher the requirements for its spectral purity, i.e. it is necessary to generate an especially spectrally pure clock signal. It requires significant technical outlay to distribute the low-jitter clock signal, which is usually generated centrally, within the entire system by means of multi-channel solutions without compromising the spectral purity of the clean clock signal generated at such expense.
Conventional systems which require a particularly high resolution during the digital to analogue conversion, such as ADSL transceivers or systems for example, or which require a wide signal bandwidth to be processed, such as VDSL systems for example, require highly accurate clock signals with very low jitter in the order of 5 ps to 15 ps RMS, which are generated by LC-PLL circuits for example. The required accuracy of the clock signal depends on the resolution of the digital/analogue converter and on other signal properties such as the crest factor and the maximum signal frequency to be processed for example. The maximum permitted jitter is calculated by means of a predetermined signal-to-noise ratio SNR in accordance with the following rule of thumb:
      TJitter    RMS    =            10                        -          SNR                ·        20                    2      ⁢                          ⁢      π      ⁢                          ⁢              f                  analog          ⁢                                          ⁢          max                    
A disadvantage of the conventional arrangement shown in FIG. 1 is that technically it is very costly to implement high-quality LC-PLL circuits that supply a low-jitter clock signal and they take up a lot of space when integrated on a chip. Moreover, high-quality LC-PLL circuits use a relatively large amount of power during operation, which creates undesired heat.